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HGA: A Hardware-Based Genetic Algorithm. Authors: S.D.Scott, A.Samal, S.Seth
Published in Conference on 12-14 Feb. 1995
Abstrat:
This article describes the implementation of a hardware-based genetic algorithm (HGA) and demonstrates how the use of reprogrammable FPGA can improve the system performance. They show an hardware implementation and a performance comparison with software implementation. Unfortunately, this article does not take care of the dynamic partial reconfiguration, it only considers the FPGA re-programmability. -
An FPGA Implementation of the TwoDimensional FiniteDifference TimeDomain (FDTD) Algorithm. Authors:W.Chen, P.Kosmas, M.Leeser, C.Rappaport
Published in Conference on January 2004
Abstract
In this article, a powerful computational electromagnetic technique for modelling the electromagnetic space has been presented. In order to increase the computational speed, a hardware implementation has been developed. Also, a comparison between the HW and SW performances has been presented but does not talk about the dynamic partial reconfiguration. -
A MULTI-PLATFORM CONTROLLER ALLOWING FOR MAXIMUM DYNAMIC PARTIAL RECONFIGURATION THROUGHPUT. Authors: C.Claus, L.Braun
Published in a conference on 8-10 Sept. 2008
This paper shows the implementation of an on-chip configuration controller(ICAP controller) for a dynamic partial reconfiguration (DPR). It is useful since presents a method to compute the reconfiguration time and a throughput. The developed ICAP controller has been compared, measuring the throughput and the reconfiguration time, with an existing ICAP controller using two different devices: the Virtex-II and Virtex-4 as devices. -
OLLAF : A dual plane reconfigurable architecture for OS support. Authors: S.Garcia, B.Granado
Published in a Workshop on 20-22 Dec. 2008
Abstract
In this article, a Fine Grained Dynamically Reconfigurable Architecture (FGDR) that enhance OS services support called OLLAF has been presented. The efficiency of these architecture has been demonstrated without a metrics but only performing a comparison with an architecture that uses a traditional commercial FPGA. -
Quality of Service Profiling Authors:S.Misailovic, S.Sidiroglou, H.Hoffmann
Published in international conference on 2-8 May 2010
Abstract
This article presents a Quality of services (QoS) profiler. It is useful since providing a method to analyze the applications and to optimize it in term of performance and QoS. In the paper does not “consider” a partial reconfiguration and question is: “Is this method applicable for DPR???” -
Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model. Authors:K.PAPADIMITRIOU,A.DOLLAS,S.HAUCK
Published Journal: TRETS on 2011
Abstract
In this article a survey about t the performance of the factors that contribute to the reconfiguration speed have been presented. This it is useful since explaining in detail the reconfiguration architecture and how to compute the reconfiguration time and throughput. Although the article refers to 2011 it reports the reconfiguration time measuring about the most representative works. -
Execution Modeling in Self-Aware FPGA-Based Architectures for Efficient Resource Management. Authors:A.Rodrıguez, J.Valverde, C.Castanares, J.Portilla, E.De la Torre, T.Riesgo
Published in Conference on 29 June-1 July 2015
Abstract:
This paper present a model for dynamic resource management.This paper is useful since a present a model that can be used by the Dynamic Resource manager to generate efficient allocation and scheduling policies taking in to account some parameters.The focus is on power consumption although during the reconfiguration it does not calculate, a fixed value is used. Some limitations of reconfiguration performance are listed but do not solve. -
A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs. Authors:A.Biondi, A.Balsini, M.Pagani, E.Rossi, M.Marinoni, G.Buttazzo
Published in conference on 29 Nov.-2 Dec. 2016
Abstrac:
This article presents a new framework that exploits HW accelerators developed through FPGA with DPR capabilities. The proposed framework is able to calculate the reconfiguration time, execution time and response time. But it is proposed to supporting the development of the safety-critical real-time application. Indeed the response-time analysis real-time constraints are used. -
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. Authors: A.Rodríguez, Juan Valverde,J.Portilla, A.Otero,T. Riesgo,E.De la Torre
Published at journals on 8 June 2018
Abstarct:
The paper presents an integrated framework to design the adaptive high-performance embedded systems for edge computing. The proposed approach provides a hardware-based processing architecture called ARTICo3 and the required tools, at both design time and run time. The paper show the framework bottlenecks and the overhead but not the reconfiguration time.